Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that its digital and custom/analog flows have achieved certification for TSMC's N3 and N4 process technologies in support of the latest Design Rule Manual (DRM). Through continued collaborations, Cadence and TSMC delivered the corresponding process design kits (PDKs) for TSMC N3 and N4 processes to accelerate mobile, AI and hyperscale computing innovation. In addition, mutual customers have already validated the benefits of the Cadence® flows and TSMC's process technologies through successful tapeouts.
To learn more about the Cadence digital and custom/analog advanced-node solutions, which support the Cadence Intelligent System Designtm strategy and enable system-on-chip (SoC) design excellence, visit www.cadence.com/go/advndtsmc34.
N3 and N4 Digital Flow Certifications
Cadence worked closely with TSMC to optimize the digital flow for TSMC's advanced N3 and N4 process technologies to help customers achieve power, performance and area (PPA) goals and speed time to market. The complete, integrated RTL-to-GDS flow includes the Cadence Innovustm Implementation System, Liberatetm Characterization Solution, Quantustm Extraction Solution, Quantus Field Solver, Tempustm Timing Signoff Solution and ECO Option, and the Voltustm IC Power Integrity Solution. Additionally, the Cadence Genustm Synthesis Solution and predictive iSpatial technology are enabled for the N3 and N4 process technologies.
The digital full flow enables customers to successfully design on TSMC's N3 and N4 process technologies through several capabilities, including:
N3 and N4 Custom/Analog Tool Suite Certification
Cadence has continued its long-standing collaboration with TSMC engineers to deliver a comprehensive custom, analog, EM-IR and mixed-signal design solution, addressing the challenges and complexities for designing custom and analog IP in TSMC's N3 and N4 process technologies. Through this collaboration, the Virtuoso® Design Platform, Spectre® Simulation Platform and the Voltus-Fi Custom Power Integrity Solution have achieved the latest TSMC N3 and N4 PDK requirements.
The custom flow for N3 and N4 process technologies make use of the following design solutions:
In addition, the Virtuoso and Spectre platforms have been certified for TSMC's N3 and N4 process technologies.
"Through our continued collaboration with Cadence, we're enabling customers to improve productivity with certified flows for our advanced N3 and N4 process technologies," said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. "This joint effort between TSMC and Cadence is making it easy for customers who are creating next-generation mobile, AI and hyperscale computing designs to achieve PPA goals and quickly launch their differentiated products to market."
"By working closely with TSMC, our customers have access to the most sophisticated capabilities to create competitive designs with TSMC's N3 and N4 process technologies and our digital flow and custom/analog flow," said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. "We continuously listen to our mutual customers to gain an understanding of their real-world design requirements, and their feedback enabled us to tailor our flows accordingly so they can achieve SoC design excellence."
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications, including consumer, hyperscale computing, 5G communications, automotive, mobile, aerospace, industrial and healthcare. For seven years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.
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